1. Field of the Invention
This invention generally relates to a static random access memory device, and in particular to a stacked static random access memory device in which active component elements are formed and arranged in two layers.
2. Description of the Prior Art
In order to have a brief background understanding on the prior art related to the field of the present invention, reference is made to FIG. 5 which schematically illustrates in block diagram the general arrangement of one prior-art static random access memory (hereinafter referred to as SRAM). As shown, the SRAM includes a plurality of memory cells 40 arrange in an array 40 for storing data signals. The SRAM also includes X and Y decoders 42 and 43 for providing signals X.sub.O -X.sub.n and Y.sub.O -Y.sub.n, respectively, to designate the memory cells 40, and a sense amplifier 44 for reading out and amplifying the data signal stored in the memory cells 40.
In FIG. 6, there is shown a circuit configuration of a typical memory cell incorporated in the conventional SRAM. The memory cell 40 includes a CMOS flip flop connected between a supply voltage V.sub.cc and a ground potential V.sub.ss, and a pair of accessing NMOS field effect transistors Q5 and Q6 connected between the flip flop and bit lines 33 and 34.
The flip flop has a pair of cross-coupled CMOS inverter. One inverter comprises a PMOS field effect transistor Q1 and an NMOS field effect transistor Q2, while the other inverter comprises a PMOS field effect transistor Q3 and an NMOS field effect transistor Q4. The accessing field effect transistors Q5 and Q6 have their gates connected to the word line 35. Conventionally, these six transistors for the SRAM cell are formed in a planar arrangement on a semiconductor substrate.
A description concerning to an operation of such SRAM cells as shown in FIG. 6 is seen, for example, on pages 356 to 358 of a textbook entitled "MICROELECTRONICS" (second edition copyrighted in 1987) authored by J. Millman et. al and published by McGraw-HILL BOOK COMPANY.
FIG. 7 shows schematically in a perspective illustration the arrangement of the six transistors for forming a memory cell on a flat semiconductor substrate. Reference characters used correspond to those in FIG. 6.
Three major layers of component parts for forming the memory cell in the flat semiconductor substrate of FIG. 7 are shown in FIGS. 8A-8C.
In a lower layer shown in FIG. 8A, there are provided n.sup.- and p.sup.- impurity diffusion regions, and coatings of gate oxide and polysilicon are successively applied over these impurity diffusion regions to form six transistors Q1-Q6. Contact portions C1-C4 indicated by the slashed designation are for interconnecting the electrodes of the transistors. The contact portions are connected by aluminum layers 31 and 32 formed in an intermediate layer of the substrate shown in FIG. 8B. The intermediate layer also has a word line 35 formed of aluminum and an interconnection 36 made of aluminum. The aluminum interconnection 36 is communicated to the supply voltage V.sub.cc. In an upper layer of the substrate shown in FIG. 8C, there are formed aluminum bit lines 33 and 34 and aluminum interconnections 37 and 38 to the ground potential V.sub.ss.
The SRAM cells have conventionally been formed in a planar arrangement on the semiconductor substrate as has been described above. However, as the cell density increases, additional structures have been incorporated into the memory device, for example, guard rings for the prevention of latch-ups, making the memory device more complex in construction. In order to overcome the problem, it has been proposed to form the SRAM memory in stacked arrangement.
In FIG. 9, there is schematically illustrated in perspective a circuit configuration of a memory cell for a prior-art double-layer stacked SRAM. The stacked SRAM of the type shown is disclosed in Japanese Laying-Open Gazette No. 32467/1986. The SRAM comprises a plurality of transistors formed and arranged in two layers on a semiconductor substrate. The transistors in different layers are interconnected via through-holes made to extend between the two layers on the substrate. The stacked SRAM is formed using Silicon-on-insulation (hereinafter refer to as SOI).
Referring to FIG. 9, on the upper or first active element layer, there are provided PMOS field effect transistors Q1 and Q3, and bit lines. 33 and 34. The first electrode of each of the transistors Q1 and Q3 is connected to the supply voltage V.sub.cc. The gate electrode of the transistor Q1 and the second electrode of the transistor Q3 are coupled together at a node N21. Similarly, the gate electrode of transistor Q3 and the second electrode of the transistor Q1 are connected together at a node N11.
Provided on the lower or second active element layer are NMOS field effect transistors Q2, Q4, Q5 and Q6 and a word line 35. Of these transistors, the transistors Q2 and Q4 have their first electrodes connected together to the ground potential V.sub.ss. The gate electrode of the transistor Q2 and the second electrode of the transistor Q4 are coupled together at a node N22, while the gate electrode of transistor Q4 and the second electrode of the transistor Q2 are linked together at a node N12.
The upper and lower layers being separated by an insulating layer (not shown) desired electrical interconnections between these layers are attained by a conductive through-holes made to extend between them. Thus, a through-hole 51 is made through the intermediate insulating layer for an electrical interconnection between the node N11 on the upper layer and the node N12 on the lower layer. Made also through the insulating layer is a through-hole 52 for an electrical interconnection between the node N21 on the upper layer and the node N22 on the lower layer. Transistors Q1, Q3, Q2 and Q4 on the different layers are interconnected via the through-holes 51 and 52 to form a CMOS flip flip.
On the second or lower layer, the accessing field effect transistor Q5 has its first electrode connected to the node N12 and its gate electrode connected to the word line 35. Similarly, the transistor Q6 has its first electrode connected to the node N22 and its gate electrode connected to the word line 35. The second electrode of transistor Q5 is coupled to the bit line 33 on the upper layer via the through-hole 53. In a similar manner, the second electrode of transistor Q6 is coupled to the bit line 34 on the upper layer via the through-hole 54.
FIGS. 10A and 10B show plane configurations of the upper and lower active layers of the SRAM cell of FIG. 9.
As shown in FIG. 10A and 10B, a p type impurity diffusion layer 55 is created in a SOI layer of the upper layer. The impurity diffusion layer 55 is covered by a gate oxide coating (not shown), on which polysilicon 60 is selectively deposited, thereby to form transistors Q1 and Q3. On the other hand, in the lower layer, a n type impurity region 56 is created in the p.sup.- region of the semiconductor substrate. The impurity region 56 is covered by a gate oxide coating (not shown), on which polysilicon 71 is selectively deposited, thereby to form transistors Q2, Q4, Q5 and Q6. Through-holes 51, 52, 53 and 54 are made to extend between the upper and lower layers as has been described hereinabove. The cross-coupled interconnections between the transistors are not shown.
With the arrangement of the prior art stacked SRAM cell shown in FIG. 9, four through-holes 51, 52, 53 and 54 are required for every memory cell. Of these through-holes, the through-holes 53 and 54 are shared by adjacent memory cells. Accordingly, the total effective area occupied by the through-holes 53 and 54 is equal to the effective area S occupied by a single through-hole. The total effective area of the through-holes 51 and 52 is equal to 2S. This brings the total area occupied by the through-holes 51, 52, 53 and 54 to 3S. A relatively large area consumed by the through-holes is a notable factor working against an increased cell density in the SRAM.
Referring to FIG. 11, there is shown in cross section a local oxidation of silicon (hereinafter refer to as LOCOS) 81 formed on the lower layer in the SRAM cell of FIG. 9 for the device isolation in the lower layer. A coating 69 of SiO.sub.2 is formed over the p.sup.- region 66 of the substrate. Applied on the SiO.sub.2 coating is a coating 68 of SiN. As can be seen in FIG. 11, the LOCOS 81 includes portions called bird's beaks extending between the SiN layer 68 and the p.sup.- substrate 66. Assuming that the thickness of the LOCOS 81 is 5,000 A, the length L1 of the bird's beak would be about 5,000 A. In the SRAM cell shown in FIG. 9, four transistors are provided in the lower layer. In order to isolate these transistors, many LOCOS regions 81 must be made, which is undesirable in terms of increasing the cell density.
FIG. 12 shows in enlarged cross-section a small portion of the SRAM cell of FIG. 9. The SOI layer 62 in the upper layer is covered by a gate oxide coating 61, on which polysilicon 60 is selectively deposited, thereby to form a field effect transistor. On the other hand, in the lower layer, a p.sup.- region 66 is created in the n-type silicon substrate 67. The p.sup.- region 66 is covered with a gate oxide coating 65, upon which polysilicon is selectively deposited to form a field effect transistor. The resulting field effect transistor is covered by an insulating coating (72), which in turn is covered with a polysilicon layer 64. The polysilicon layer 64 is connected to the drain or source of the resultant transistor. Provided between the polysilicon layer 64 and the SOI layer 62 is an insulating layer 63 for separating the upper layer from the lower layer.
The substrate through-holes 51 and 53 of FIG. 9 may be formed having different depths by etching and filling the holes with a conductive material. For the formation of holes having different depths by means of etching, the etching rates for the silicon and oxide layer must be precisely controlled to be much different from each other as required, making the fabrication process ever-more complicated.